Conventional semiconductor electronic storage devices, such as Dynamic Random Access Memory (“DRAM”) devices, typically incorporate capacitor and transistor structures in which memory cell capacitors temporarily store data based on the charged state of the capacitors. When data bits are to be written to or read from the memory cells, the memory cell capacitors are selectively coupled to digit lines through respective access transistors.
There is an ever-present desire in the semiconductor fabrication industry, in general, and the memory industry, specifically, to achieve individual devices with smaller physical dimensions. Reducing the dimensions, a process known as “scaling,” is desirable in order to increase the number of individual devices that can be placed on a given area of semiconductor material thereby reducing the unit cost and the power consumption of individual devices. In addition, scaling can result in performance increases of the individual devices as the charge carriers, having a finite velocity, have a shorter distance to travel, and they provide less bulk material for charge to accumulate or dissipate.
One method of designing smaller memory cells is to use vertical transistors, such as fin field effect transistor (“FinFET”) devices. A FinFET device employs a vertically arranged structure or fin interposed between the source and drain where the channel is defined, typically with a multi-gate configuration. The advantages of the FinFET architecture include the ability to define device dimensions smaller than the photolithographic limit and the ability to easily access opposed sides of the channel to achieve a multi-gate structure. Such a multi-gate arrangement can provide superior control over the gate of the device. A fully depleted silicon fin can be achieved with very low doping levels in the active region.
With reference to FIG. 1, a FinFET device 10 typically includes a fin 14 extending between a vertically oriented drain pillar 18 and a vertically oriented source pillar 20. The fin 14, drain pillar 18 and source pillar 20 are fabricated in a body 22 of semiconductor material. Gates 24 are fabricated on each side of the fin 14, although only one gate 24 is shown in FIG. 1.
A prior art structure for using FinFET devices 10 used as a DRAM access transistor is shown in FIG. 2. The drain pillar 18 is common to two FinFET devices 30, 32. The source pillar 20 of the first FinFET device 30 is separated from the source pillar 20 of a third FinFET device 36 through a shallow trench isolation (STI″) structure 40 fabricated in the body 22. The STI structure 40 electrically isolates the source pillar 20 of the FinFET device 30 from the source pillar 20 of the FinFET device 36. Similarly, the source pillar 20 of the second FinFET device 32 is isolated from the source pillar 20 of a fourth FinFET device 44 by a STI structure 48. The drain pillar 18 is common to two FinFET devices 30, 32, and it is connected to a common digit line 26. The source pillars 20 of the FinFET devices 30, 32, 36, 44 are connected to respective memory cell capacitors 28.
Although scaling memory devices, such as DRAMs, provide the advantages of reducing cost and power consumption, scaling is not without its performance drawbacks. In particular, scaling can increase sub-threshold leakage between the drain pillar 18 and source pillar 20. In some applications, sub-threshold leakage does not present any problems in the use of FinFET devices. However, in other applications, such as for use as access transistors, sub-threshold leakage can significantly degrade the performance of DRAM devices. The length of time that memory cell capacitors can store charge is greatly effected by the amount of sub-threshold leakage through the respective access transistors to which they are connected. Shorter charge retention times require that the memory cells be refreshed more frequently. However, refreshing memory cells consumes a significant amount of power. Therefore, excessive sub-threshold leakage of access transistors can greatly increase the amount of power consumed by DRAM devices. Furthermore, if the sub-threshold leakage is large enough, it can result in data retention errors.
A primary cause of sub-threshold leakage in FinFET devices arises from the structure that is typically used for FinFET devices. In particular, the fin 14 is connected to the body 22 of semiconductor material in which the FinFET device 10 is fabricated, which can serve as a current leakage path from a memory cell capacitor connected to the source pillar 20. This current leakage path can seriously limit the use of FinFET devices 10 for DRAM access transistors. There can also be sub-threshold leakage from the source pillar 20 directly to the body 22 and from the drain pillar 18 directly to the body. However, this leakage is of a lesser magnitude and is thus less of a problem than leakage from the fin 14 to the body 22.
There is therefore a need for a FinFET structure that reduces the sub-threshold leakage of FinFET devices, particularly between the fin and body of such devices.